Chip-package-interaction modeling of ultra low-k/copper back end of line
- X.-H. Liu
- T.M. Shaw
- et al.
- 2007
- IITC 2007
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48 results for Xiao Hu Liu
Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates
- Haizhou Yin
- Z. Ren
- et al.
- 2006
- VLSI Technology 2006
65nm Cu integration and interconnect reliability in low stress K=2.75 SiCOH
- V. McGahay
- G. Bonilla
- et al.
- 2006
- IITC 2006
Theory for electromigration failure in Cu conductors
- J.R. Lloyd
- C.E. Murray
- et al.
- 2005
- International Workshop on Stress-Induced Phenomena in Metallization 2005
Analysis and modeling of curvature in copper-based mems structures fabricated using CMOS interconnect technology
- Marie-Ange Eyoum
- Nils Hoivik
- et al.
- 2005
- TRANSDUCERS 2005
Low-k BEOL mechanical modeling
- Xiao Hu Liu
- Michael W. Lane
- et al.
- 2004
- ADMETA 2004
Chip-to-Package Interaction for a 90 nm Cu / PECVD Low-k technology
- W. Landers
- D. Edelstein
- et al.
- 2004
- IITC 2004
90 nm SiCOH technology in 300 mm manufacturing
- L. Clevenger
- M. Yoon
- et al.
- 2004
- ADMETA 2004
Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL
- D. Edelstein
- H.S. Rathore
- et al.
- 2004
- IRPS 2004
Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL
- D. Edelstein
- H.S. Rathore
- et al.
- 2004
- IRPS 2004