Charge trapping in aggressively scaled metal gate/high-κ stacks
- E. Gusev
- V. Narayanan
- et al.
- 2004
- IEDM 2004
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45 results for M. Chudzik
Inversion channel mobility in high-κ high performance MOSFETs
- Z. Ren
- M.V. Fischetti
- et al.
- 2003
- IEDM 2003
Titanium silicide/titanium nitride full metal gates for dual-channel gate-first CMOS
- Martin M. Frank
- Cyril Cabral
- et al.
- 2016
- IEEE Electron Device Letters
1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
- Rajesh Rengarajan
- Boyong He
- et al.
- 2002
- IEEE Electron Device Letters
Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures
- Nicolas Breil
- A. Carr
- et al.
- 2017
- VLSI Technology 2017
Deposited ALD SiO2 high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- S. Siddiqui
- M.M. Chowdhury
- et al.
- 2013
- ECS Meeting 2013
Hybrid clean approach for post-copper CMP defect reduction
- Wei-Tsu Tseng
- Vamsi Devarapalli
- et al.
- 2013
- ASMC 2013
Characterization and optimization of charge trapping in high-k dielectrics
- Eduard Cartier
- Takashi Ando
- et al.
- 2013
- IRPS 2013
Optimization of Cu damascene electrodeposition process in ULSI for yield and reliability improvement
- Ingrid Shao
- T. Cheng
- et al.
- 2013
- ECS Transactions
Bias temperature instability in high-κ/metal gate transistors - Gate stack scaling trends
- Siddarth Krishnan
- Vijay Narayanan
- et al.
- 2012
- IRPS 2012