L.K. Wang, A. Acovic, et al.
MRS Spring Meeting 1993
We report a new N/PFET Gate Patterning Boundary Proximity layout dependent effect in high-k dielectric/Metal Gate (HK/MG) MOSFETs which causes anomalous threshold voltage (Vt) modulation for the first time. We investigated the mechanism by using special test structures and process optimizations to suppress this layout dependency. Finally, we achieved the best over all process optimization which makes it possible to suppress layout dependency without degrading FET performance/yield/reliability. © 2011 IEEE.
L.K. Wang, A. Acovic, et al.
MRS Spring Meeting 1993
Shu-Jen Han, Alberto Valdes-Garcia, et al.
IEDM 2011
Sharee J. McNab, Richard J. Blaikie
Materials Research Society Symposium - Proceedings
J.A. Barker, D. Henderson, et al.
Molecular Physics