Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- Chen Zhang
- Seungmin Song
- et al.
- 2024
- IEDM 2024
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6 results for Shanti Pancharatnam
Novel ellipsometry-based machine learning technique for characterization of low sensitivity critical dimensions within gate-all-around transistors
- Houssam Chouaib
- Valeria Dimastrodonato
- et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors
- Curtis Durfee
- Ivo Otto
- et al.
- 2023
- ECS Meeting 2023
Epi Source/Drain Damage Mitigation with Inner Spacer and Buffer Optimization in Stacked Nanosheet Gate-All-Around Transistors
- Curtis Durfee
- Ivo Otto
- et al.
- 2023
- SSDM 2023
Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
- Curtis Durfee
- Subhadeep Kal
- et al.
- 2021
- ECS Meeting 2021
Development of SiGe Indentation Process Control for Gate-All-Around FET Technology Enablement
- Daniel Schmidt
- Aron Cepler
- et al.
- 2022
- IEEE Trans Semicond Manuf