Evaluation of device damage from e-beam curing of ultra low-k BEOL dielectrics
- S. Mehta
- C. Dimitrakopoulos
- et al.
- 2005
- AMC 2005
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20 results for Anthony Chou
Synthesis and control of ultra thin gate oxides for the 90 and 65 NM nodes
- Joseph F. Shepard Jr.
- Anthony Chou
- et al.
- 2005
- RTP 2005
Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates
- J.H. Stathis
- R. Bolam
- et al.
- 2005
- INFOS 2005
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Thermally robust dual-work function ALD-MN x MOSFETs using conventional CMOS process flow
- D.-G. Park
- Z. Luo
- et al.
- 2004
- VLSI Technology 2004
Broad energy distribution of NBTI-induced interface states in p-MOSFETs with ultra-thin nitrided oxide
- J.H. Stathis
- G. LaRosa
- et al.
- 2004
- IRPS 2004
Broad energy distribution of NBTI-induced interface states in p-MOSFETs with ultra-thin nitrided oxide
- J.H. Stathis
- G. Larosa
- et al.
- 2004
- IRPS 2004
High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations
- M. Yang
- M. Ieong
- et al.
- 2003
- IEDM 2003
Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics
- Min Yang
- Evgeni P. Gusev
- et al.
- 2003
- IEEE Electron Device Letters
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002