Backward compatible connectors for next generation PCIe electrical I/O
- Lei Shan
- Daniel Freidman
- et al.
- 2018
- ECTC 2018
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43 results for Lei Shan
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
Organic Multi-Chip Module for high performance systems
- Lei Shan
- Young Kwark
- et al.
- 2015
- ECTC 2015
High performance packaging laminates enable buses for exascale systems
- Lei Shan
- Young Kwark
- et al.
- 2015
- DesignCon 2015
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
Preparing 25Gbps electrical I/O for exascale computing systems
- Lei Shan
- Young Kwark
- et al.
- 2014
- ECTC 2014
Modeling on-board via stubs and traces in high-speed channels for achieving higher data bandwidth
- Ki Jin Han
- Xiaoxiong Gu
- et al.
- 2014
- IEEE Transactions on CPMT
Signal and power integrity (SPI) co-analysis for high-speed communication channels
- Renato Rimolo-Donadio
- Xiaomin Duan
- et al.
- 2013
- DesignCon 2013
Realization of ultra-low power I/O
- Lei Shan
- Timothy Dickson
- et al.
- 2013
- ECTC 2013
Findings and considerations for I/O clock jitter on a source synchronous front side bus
- Daniel Dreps
- Len Daniels
- et al.
- 2012
- EPEPS 2012