Ankur Agrawal, John Bulzacchelli, et al.
ISSCC 2012
A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels without loss of bandwidth. Transceiver circuit innovations are described including a low-skew transmission-line clock distribution, a 4 serializer with quadrature quarter-rate clocks, and a phase rotator based on current-integrating phase interpolators. Measurements of a test chip fabricated in 32 nm SOI CMOS technology demonstrate 1.4 pJ/b efficiency over 0.75" Megtron-6 PCB traces, and 1.9 pJ/b efficiency over 20" Megtron-6 PCB traces.
Ankur Agrawal, John Bulzacchelli, et al.
ISSCC 2012
Byungsub Kim, Yong Liu, et al.
IEEE Journal of Solid-State Circuits
Sergey V. Rylov
IEEE TAS
Zeynep Toprak-Deniz, Timothy O. Dickson, et al.
VLSI Technology and Circuits 2024