Resonant clock mega-mesh for the IBM z13™
- David Shan
- Phillip Restle
- et al.
- 2015
- VLSI Circuits 2015
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26 results for Thomas Bucelot
Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor
- Phillip Restle
- David Shan
- et al.
- 2014
- ISSCC 2014
On-chip circuit for measuring multi-GHz clock signal waveforms
- Keith A. Jenkins
- P. Restle
- et al.
- 2013
- VTS 2013
A resonant global clock distribution for the cell broadband engine processor
- Steven C. Chan
- Phillip J. Restle
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
Timing derived current for signal net reliability assessment
- Jiedong Diao
- Jim Venuto
- et al.
- 2005
- VMIC 2005
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution
- G.G. Lopez
- G. Fiorenza
- et al.
- 2005
- GLSVLSI 2005
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
- Xuejue Huang
- Phillip Restle
- et al.
- 2003
- IEEE Journal of Solid-State Circuits
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design
- Xuejue Huang
- Phillip Restle
- et al.
- 2002
- Proceedings of the Custom Integrated Circuits Conference
Infrastructure requirements for a large-scale, multi-site VLSI development project
- Gregory P. Rodgers
- Isidore G. Bendrihem
- et al.
- 2002
- IBM J. Res. Dev
CPAM: A common power analysis methodology for high-performance VLSI design
- J.Scott Neely
- Howard H. Chen
- et al.
- 2000
- IEEE Topical Meeting EPEPS 2000