Publications

50 results for Greg Freeman

Optimizing history effects in 65nm PD-SOI CMOS
- - Q. Liang
  - T. Kawamura
  - et al.
- 2006
- IEEE International SOI Conference 2006
SiGe HBT without Selectively Implanted Collector (SIC) exhibiting f _max = 310 GHz and BV_CEo = 2 v
- - Jae-Sung Rieh
  - Marwan Khater
  - et al.
- 2006
- IEEE Transactions on Electron Devices
Structure optimization of trench-isolated SiGe HBTs for simultaneous improvements in thermal and electrical performances
- - Jae-Sung Rieh
  - David Greenberg
  - et al.
- 2005
- IEEE Transactions on Electron Devices
High-performance silicon-germanium technology
- - Seshadri Subbanna
  - Greg Freeman
  - et al.
- 2005
- DRC 2005
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- - E. Leobandung
  - H. Nayakama
  - et al.
- 2005
- VLSI Technology 2005
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- - W.-H. Lee
  - A. Waite
  - et al.
- 2005
- IEDM 2005
Reverse active mode current characteristics of SiGe HBTs
- - Jae-Sung Rieh
  - Jin Cai
  - et al.
- 2005
- IEEE Transactions on Electron Devices
Scaling of SiGe heterojunction bipolar transistors
- - Jae-Sung Rieh
  - Andreas Stricker
  - et al.
- 2005
- Proceedings of the IEEE
Proton radiation response of monolithic millimeter-wave transceiver building blocks implemented in 200 GHz SiGe technology
- - Wei-Min Lance Kuo
  - Yuan Lu
  - et al.
- 2004
- IEEE TNS
RFCMOS technology from 0.25μm to 65nm: The state of the art
- - J.J. Pekarik
  - D.R. Greenberg
  - et al.
- 2004
- CICC 2004