Induced e-beam charge impact on spatial orientation of gate-All-Around silicon wires device fabricated on boron nitride substrate
- Shimon Levi
- Konstantin Chirko
- et al.
- 2015
- SPIE Advanced Lithography 2015
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47 results for Leathen Shi
CD-SEM metrology evaluation of gate-all-around Si nanowire MOSFET with improved control of nanowire suspension by using a buried boron nitride etch-stop layer
- Guy M. Cohen
- Leathen Shi
- et al.
- 2014
- ASMC 2014
Epitaxial lift-off process for gallium arsenide substrate reuse and flexible electronics
- Cheng-Wei Cheng
- Kuen-Ting Shiu
- et al.
- 2013
- Nature Communications
FDSOI CMOS with dielectrically-isolated back gates and 30nm LG high-κ/metal gate
- Marwan Khater
- J. Cai
- et al.
- 2010
- VLSI Technology 2010
Experimental and theoretical explanation for the orientation dependence gate-induced drain leakage in scaled MOSFETs
- P. Solomon
- S.E. Laux
- et al.
- 2009
- DRC 2009
FDSOI CMOS with dual backgate control for performance and power modulation
- Jeng-Bang Yau
- Jin Cai
- et al.
- 2009
- VLSI-TSA 2009
Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding
- R.R. Yu
- F. Liu
- et al.
- 2009
- VLSI Technology 2009
A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid cu-adhesive bonding
- F. Liu
- R.R. Yu
- et al.
- 2008
- IEDM 2008
Wafer-level 3D integration technology
- Steven J. Koester
- Albert M. Young
- et al.
- 2008
- IBM J. Res. Dev
Critical aspects of layer transfer and alignment tolerances for 3D integration processes
- D.C. La Tulipe
- L.T. Shi
- et al.
- 2006
- GBC 2006