Ziyang Liu, Sivaramakrishnan Natarajan, et al.
VLDB
An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed. © Copyright 2008 by International Business Machines Corporation.
Ziyang Liu, Sivaramakrishnan Natarajan, et al.
VLDB
Arun Viswanathan, Nancy Feldman, et al.
IEEE Communications Magazine
Yigal Hoffner, Simon Field, et al.
EDOC 2004
John M. Boyer, Charles F. Wiecha
DocEng 2009