Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009
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61 results for Leland Chang
Low power circuit design based on heterojunction tunneling transistors (HETTs)
- Daeyeon Kim
- Yoonmyung Lee
- et al.
- 2009
- ISLPED 2009
Operational amplifier based test structure for quantifying transistor threshold voltage variation
- Brian L. Ji
- Dale J. Pearson
- et al.
- 2009
- IEEE Trans Semicond Manuf
Demonstration of highly scaled FinFET SRAM cells with high-Κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond
- H. Kawasaki
- M. Khater
- et al.
- 2008
- IEDM 2008
Operational amplifier based test structure for transistor threshold voltage variation
- Brian L. Ji
- Dale J. Pearson
- et al.
- 2008
- ICMTS 2008
An analytical model for intrinsic carbon nanotube FETs
- Lan Wei
- David J. Frank
- et al.
- 2008
- ESSDERC 2008
An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches
- Leland Chang
- Robert K. Montoye
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
A 5.3GHz 8T-SRAM with operation down to 0.41V in 65nm CMOS
- Leland Chang
- Yutaka Nakamura
- et al.
- 2007
- VLSI Circuits 2007
VDD scaling for FinFET logic and memory circuits: The impact of process variations and SRAM stability
- C.-H. Lin
- K. Das
- et al.
- 2006
- VLSI-TSA 2006
Silicon-on-insulator MOSFETs with hybrid crystal orientations
- M. Yang
- K.K. Chan
- et al.
- 2006
- VLSI Technology 2006