Wafer-level 3D integration technology
- Steven J. Koester
- Albert M. Young
- et al.
- 2008
- IBM J. Res. Dev
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56 results for M. Wordeman
Destructive-read Random Access Memory System Buffered with Destructive-read Memory Cache for SoC Applications
- Brian L. Ji
- Seiji Munetoh
- et al.
- 2003
- VLSI Circuits 2003
1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- O. Takahashi
- S. Dhong
- et al.
- 2000
- ISSCC 2000
1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro
- Osamu Takahashi
- Sang H. Dhong
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's
- Heinz Hoenigschmid
- Alexander Frey
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
- Toshiaki Kirihata
- Martin Gall
- et al.
- 1998
- IEEE Journal of Solid-State Circuits
220 mm2 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture
- T. Kirihata
- M. Gall
- et al.
- 1998
- ISSCC 1998
Development of a high bandwidth merged logic/DRAM multimedia chip
- W.K. Luk
- Y. Katayama
- et al.
- 1997
- ICCD 1997
Flexible test mode approach for 256-Mb DRAM
- Toshiaki Kirihata
- Hing Wong
- et al.
- 1997
- IEEE Journal of Solid-State Circuits
Flexible test mode design for DRAM characterization
- H. Wong
- T. Kirihata
- et al.
- 1996
- VLSI Circuits 1996