A 34&181;m2DRAM cell fabricated with a 1&181;m single-level polycide FET technology
- Hu H. Chao
- Robert H. Dermard
- et al.
- 1981
- ISSCC 1981
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56 results for M. Wordeman
A New “Shift and Ratio” Method for MOSFET Channel-Length Extraction
- Yuan Taur
- D.S. Zicherman
- et al.
- 1992
- IEEE Electron Device Letters
Hot-Electron-Induced Instability in 0.5-μm p-Channel MOSFET’s Patterned Using Synchrotron X-ray Lithography
- C.C.-H. Hsu
- L.K. Wang
- et al.
- 1989
- IEEE Electron Device Letters
Inverter Performance Of Deep-Submicrometer Mosfet'S
- George A. Sai-Halasz
- Matthew R. Wordeman
- et al.
- 1988
- IEEE Electron Device Letters
High Transconductance and Velocity Overshoot in NMOS Devices at the 0.1-μm Gate-Length Level
- George A. Sai-Halasz
- Matthew R. Wordeman
- et al.
- 1988
- IEEE Electron Device Letters
Design and Experimental Technology for 0.1-μm Gate-Length Low-Temperature Operation FET's
- George A. Sai-Halasz
- Matthew R. Wordeman
- et al.
- 1987
- IEEE Electron Device Letters
Geometry Effects in MOSFET Channel Length Extraction Algorithms
- M.R. Wordeman
- J.Y.-C. Sun
- et al.
- 1985
- IEEE Electron Device Letters
Monte Carlo Modeling of the Transport of Ionizing Radiation Created Carriers in Integrated Circuits
- G.A. Sai-Halasz
- M.R. Wordeman
- 1980
- IEEE Electron Device Letters
Analytical test of 3D integrated circuits
- Raphael P. Robertazzi
- Micheal Scheurman
- et al.
- 2017
- ITC 2017
Thermal analysis of multi-layer functional 3D logic stacks
- Michael Scheuermann
- Shurong Tian
- et al.
- 2016
- 3DIC 2016