Double spin-torque magnetic tunnel junction devices for last-level cache applications
- G. Hu
- C. Safranski
- et al.
- 2022
- IEDM 2022
Publications
Date
Featured collections
Popular topics
75 results for Christopher P. D’Emic
Reliable Sub-nanosecond MRAM with Double Spin-torque Magnetic Tunnel Junctions
- C. Safranski
- G. Hu
- et al.
- 2022
- VLSI Technology and Circuits 2022
Demonstration of narrow switching distributions in STT-MRAM arrays for LLC applications at 1x nm node
- E. R.J. Edwards
- Guohan Hu
- et al.
- 2020
- IEDM 2020
Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications
- Guohan Hu
- D. Kim
- et al.
- 2019
- IEDM 2019
High Performance InGaAs Gate-All-Around Nanosheet FET on Si Using Template Assisted Selective Epitaxy
- S. Lee
- Cheng-Wei Cheng
- et al.
- 2018
- IEDM 2018
Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs
- H. Miki
- N. Tega
- et al.
- 2012
- IEDM 2012
Complementary thin-base symmetric lateral bipolar transistors on SOI
- Jin Cai
- Tak H. Ning
- et al.
- 2011
- IEDM 2011
Hysteretic drain-current behavior due to random telegraph noise in scaled-down FETs with high-κ/metal-gate stacks
- Hiroshi Miki
- Naoki Tega
- et al.
- 2010
- IEDM 2010
Reduction of random telegraph noise in high-κ / metal-gate stacks for 22 nm generation FETs
- N. Tega
- H. Miki
- et al.
- 2009
- IEDM 2009
Extendibility of NiPt silicide contacts for CMOS technology demonstrated to the 22-nm node
- Kazuya Ohuchi
- Christian Lavoie
- et al.
- 2007
- IEDM 2007