Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitances
- Elbert Huang
- Eric Joseph
- et al.
- 2008
- IEEE International SOI Conference 2008
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178 results for Wilfried Haensch
Will SOI have a life for the low-power market?
- Jin Cai
- Zhibin Ren
- et al.
- 2008
- IEEE International SOI Conference 2008
Measurement of silicon nanowires carrier mobility and its size dependence
- O. Gunawan
- L. Sekaric
- et al.
- 2008
- DRC 2008
FinFET performance advantage at 22nm: An AC perspective
- M. Guillorn
- J. Chang
- et al.
- 2008
- VLSI Technology 2008
A 5.3GHz 8T-SRAM with operation down to 0.41V in 65nm CMOS
- Leland Chang
- Yutaka Nakamura
- et al.
- 2007
- VLSI Circuits 2007
An n-FET with a Si nanowire channel and doped epitaxially-thickened source and drain regions
- G.M. Cohen
- P. Solomon
- et al.
- 2007
- DRC 2007
35nm SOI-CMOS for sub-ambient temperature operation
- Cai Jin
- David J. Frank
- et al.
- 2007
- VLSI-TSA 2007
Simulation study of multiple FIN FinFET design for 32nm technology node and beyond
- Xinlin Wang
- Andres Bryant
- et al.
- 2007
- SISPAD 2007
Ultra-thin SOI CMOS using laser spike anneal
- Zhibin Ren
- J. Sleight
- et al.
- 2006
- VLSI-TSA 2006
VDD scaling for FinFET logic and memory circuits: The impact of process variations and SRAM stability
- C.-H. Lin
- K. Das
- et al.
- 2006
- VLSI-TSA 2006