Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source
- M.V. Fischetti
- S. Jin
- et al.
- 2009
- IWCE 2009
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83 results for Yuan Taur
Supply voltage strategies for minimizing the power of CMOS processors
- Jin Cai
- Yuan Taur
- et al.
- 2002
- VLSI Technology 2002
New polysilicon disposable sidewall process for sub-50 nm CMOS
- K.L. Lee
- D. Boyd
- et al.
- 2001
- ESSDERC 2001
Monte Carlo modeling of threshold variation due to dopant fluctuations
- D.J. Frank
- Y. Taur
- et al.
- 1999
- VLSI Technology 1999
Monte Carlo modeling of threshold variation due to dopant fluctuations
- D.J. Frank
- Y. Taur
- et al.
- 1999
- VLSI Circuits 1999
1.0-V and 1.5-V operation of 4-GHz tuned amplifiers implemented in a 0.1-μm CMOS technology on bulk and SOI substrates
- Yo-Chuol Ho
- C. Wann
- et al.
- 1998
- SiRF 1998
Asymmetry in effective-channel length of n- and p-MOSFETs
- L.R. Logan
- Y. Taur
- et al.
- 1997
- SISPAD 1997
Modeling and characterization of n+- and p+-polysilicon-gated ultra-thin oxides (21-26 angstroms)
- S.H. Lo
- D.A. Buchanan
- et al.
- 1997
- VLSI Technology 1997
Single pulse output of partially depleted SOI FETs
- Keith A. Jenkins
- Y. Taur
- et al.
- 1996
- IEEE International SOI Conference 1996
Ultra-thin, highly uniform thin film SOI MOSFET with low series resistance using pattern-constrained epitaxy (PACE)
- H.-S. Wong
- K.K. Chan
- et al.
- 1996
- VLSI Technology 1996