Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
- Sungjae Lee
- J. Johnson
- et al.
- 2012
- VLSI Technology 2012
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12 results for R. Williams
A Simple, unified 3D stress model for device design in stress-enhanced mobility technologies
- Arvind Kumar
- Kai Xiu
- et al.
- 2012
- SISPAD 2012
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
- Chung-Hsun Lin
- Wilfried Haensch
- et al.
- 2011
- VLSI Technology 2011
Statistical evaluation of split gate opportunities for improved 8T/6T column-decoupled SRAM cell yield
- Rouwaida Kanj
- Rajiv Joshi
- et al.
- 2008
- ISQED 2008
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies
- Rajiv Joshi
- Rouwaida Kanj
- et al.
- 2007
- ISLPED 2007
A high-performance, low leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2007
- VLSID 2007
SOI CMOS technology with 360GHz fT NFET, 260GHz fT PFET, and record circuit performance for millimeter-wave digital and analog system-on-chip applications
- Sungjae Lee
- Jonghae Kim
- et al.
- 2007
- VLSI Technology 2007
Modeling single-event upsets in 65-nm silicon-on-insulator semiconductor devices
- A.J. KleinOsowski
- Phil Oldiges
- et al.
- 2006
- IEEE TNS
Modeling of variation in submicrometer CMOS ULSI technologies
- Scott K. Springer
- Sungjae Lee
- et al.
- 2006
- IEEE Transactions on Electron Devices
SOI 90-nm ring oscillator sub-ps model-hardware correlation and parasitic-aware optimization leading to 1.94-ps switching delay
- Jean-Olivier Plouchart
- Jonghae Kim
- et al.
- 2005
- IEDM 2005