High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
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19 results for A.C. Mocuta
Direct temperature measurement for VLSI circuits and 3-D modeling of self-heating in sub-0.13 μm SOI technologies
- R.V. Joshi
- S.S. Kang
- et al.
- 2005
- VLSID 2005
Retardation of arsenic diffusion in silicon-germanium by co-implantation
- Omer Dokumaci
- Paul Ronsheim
- et al.
- 2004
- ECS Meeting 2004
Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
Strained Si CMOS (SS CMOS) technology: Opportunities and challenges
- K. Rim
- R. Anderson
- et al.
- 2003
- Solid-State Electronics
Mobility enhancement in strained Si NMOSFETs with HfO2 gate dielectrics
- K. Rim
- E. Gusev
- et al.
- 2002
- VLSI Technology 2002
Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs
- K. Rim
- J.O. Chu
- et al.
- 2002
- VLSI Technology 2002
Novel high-performance analog devices for advanced low-power high-k metal gate complementary metal-oxide-semiconductor technology
- Jin-Ping Han
- Takashi Shimizu
- et al.
- 2011
- Japanese Journal of Applied Physics
Ultrathin high-K gate stacks for advanced CMOS devices
- E. Gusev
- D.A. Buchanan
- et al.
- 2001
- Technical Digest - International Electron Devices Meeting