Self-annealing effect of tensile liner on thick-Tinv PMOS
- Qintao Zhang
- Jie Chen
- et al.
- 2011
- IEEE T-ED
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34 results for M. Sherony
New layout dependency in high-k/metal gate MOSFETs
- M. Hamaguchi
- Deleep R. Nair
- et al.
- 2011
- IEDM 2011
Novel high-performance analog devices for advanced low-power high-k metal gate complementary metal-oxide-semiconductor technology
- Jin-Ping Han
- Takashi Shimizu
- et al.
- 2011
- Japanese Journal of Applied Physics
Performance elements for 28nm gate length bulk devices with gate first high-k metal gate
- Jun Yuan
- C. Gruensfelder
- et al.
- 2010
- ICSICT 2010
Stress liner proximity technique to enhance carrier mobility in high-κ metal gate MOSFETs
- Dechao Guo
- Kathryn Schonenberg
- et al.
- 2009
- MRS Fall Meeting 2009
High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
- D.-G. Park
- K. Stein
- et al.
- 2009
- VLSI-TSA 2009
32nm general purpose bulk CMOS technology for high performance applications at low voltage
- F. Arnaud
- J. Liu
- et al.
- 2008
- IEDM 2008
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
- X. Chen
- S. Samavedam
- et al.
- 2008
- VLSI Technology 2008
Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
65nm CMOS technology for low power applications
- A. Steegen
- R. Mo
- et al.
- 2005
- IEDM 2005