A Novel Graded Antireflective Coating with Built-in Hardmask Properties Enabling 65nm and Below CMOS Device PatterningK. BabichN. Fukiageet al.2003IEDM 2003
Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)Jakub KedzierskiDiane Boydet al.2003IEDM 2003
Investigation of Scaling Methodology for Strained Si n-MOSFETs Using a Calibrated Transport ModelHasan M. NayfehJudy L. Hoytet al.2003IEDM 2003
High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal OrientationsM. YangM. Ieonget al.2003IEDM 2003
Thousands of Microcantilevers for Highly Parallel and Ultra-dense Data StorageP. VettigerT.R. Albrechtet al.2003IEDM 2003