Nanbo Gong, W. Chien, et al.
VLSI Technology 2020
We present a scaling study toward lZnm node 3D Cross-point PCM (XPCM) for Storage Class Memory (SCM) applications. The low operation current, and low metal line loading resistance are desired to avoid a wide operation voltage distribution in a cross-point array. For the first time, AC threshold voltage (Vth) of 1S1R OTS-PCM was studied, which will impact the operation scheme. To achieve Tera bits per chip density, six layers 1Znm 3D XPCM with OTS showing high Vth and low leakage current, and scalable periphery circuit are required.
Nanbo Gong, W. Chien, et al.
VLSI Technology 2020
Choonghyun Lee, Shogo Mochizuki, et al.
VLSI Technology 2019
Huai-Yu Cheng, W. Chien, et al.
IEDM 2017
W. Chien, E. Lai, et al.
IMW 2023