A. Ney, R. Rajaram, et al.
Journal of Magnetism and Magnetic Materials
This paper discusses the electrostatic discharge (ESD) robustness in silicon-on-insulator (SOI) high-pin-count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes without the need for additional masking steps, process implants or ESD design area. © 2000 Elsevier Science B.V.
A. Ney, R. Rajaram, et al.
Journal of Magnetism and Magnetic Materials
U. Wieser, U. Kunze, et al.
Physica E: Low-Dimensional Systems and Nanostructures
T. Schneider, E. Stoll
Physical Review B
P. Martensson, R.M. Feenstra
Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films