Conference paper
True 3-D displays for avionics and mission crewstations
Elizabeth A. Sholler, Frederick M. Meyer, et al.
SPIE AeroSense 1997
This paper discusses the electrostatic discharge (ESD) robustness in silicon-on-insulator (SOI) high-pin-count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes without the need for additional masking steps, process implants or ESD design area. © 2000 Elsevier Science B.V.
Elizabeth A. Sholler, Frederick M. Meyer, et al.
SPIE AeroSense 1997
Robert W. Keyes
Physical Review B
J.H. Kaufman, Owen R. Melroy, et al.
Synthetic Metals
J.C. Marinace
JES