Thomas H. Baum, Carl E. Larson, et al.
Journal of Organometallic Chemistry
This paper discusses the electrostatic discharge (ESD) robustness in silicon-on-insulator (SOI) high-pin-count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes without the need for additional masking steps, process implants or ESD design area. © 2000 Elsevier Science B.V.
Thomas H. Baum, Carl E. Larson, et al.
Journal of Organometallic Chemistry
Ellen J. Yoffa, David Adler
Physical Review B
J.V. Harzer, B. Hillebrands, et al.
Journal of Magnetism and Magnetic Materials
Arvind Kumar, Jeffrey J. Welser, et al.
MRS Spring 2000