23 ps/2.1 mW ECL gate
Kai-Yap Toh, C.T. Chuang, et al.
ISSCC 1989
A new shallow trench process for isolation of bipolar devices is shown to allow butting of the emitter-base junction to the field oxide edge, thereby greatly reducing the overall device size and parasitic capacitances. ECL ring-oscillator measurements demonstrate a significant performance leverage, where a delay of 75 ps is obtained at a power of 1.5 mW per gate (power-delay product of 112 fJ), an improvement of 17% from the nonbutted case. In addition, more conventional nonbutted devices have been fabricated with dopant profiles tailored to reduce intrinsic and extrinsic capacitances. These high-performance designs achieve ECL gate delays as small as 26 ps at 5.3 mW, comparable to the fastest ECL delays reported to date. © 1991 IEEE
Kai-Yap Toh, C.T. Chuang, et al.
ISSCC 1989
E. Ganin, T.C. Chen, et al.
IEDM 1990
Y. Taur, S.J. Wind, et al.
IEDM 1993
B.T. Jonker, L.P. Fu, et al.
Journal of Electronic Materials