Conference paper
Analyzing path delays for accelerated testing of logic chips
Emily Ray, Barry P. Linder, et al.
IRPS 2015
A technique is presented to measure the temperature of a large, dense, CMOS clock buffer while it is operating. The technique uses the subthreshold slope of a single pFET, thereby avoiding introducing special technology enhancements for thermal sensing, and uses purely simple electrical measurements. The technique is demonstrated to work in the presence of high-frequency digital switching in a realistic test site fabricated in a 14 nm finFET technology.
Emily Ray, Barry P. Linder, et al.
IRPS 2015
Keith A. Jenkins, Anup P. Jose, et al.
ESSCIRC 2005
Keith A. Jenkins
CSSP
Yu-Ming Lin, Alberto Valdes-Garcia, et al.
Science