A fully-integrated switched-capacitor 2:1 Voltage converter with regulation capability and 90% efficiency at 2.3A/mm2
- Leland Chang
- Robert K. Montoye
- et al.
- 2010
- VLSI Circuits 2010
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43 results for Kevin G. Stawiasz
A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS
- Masood Qazi
- Kevin Stawiasz
- et al.
- 2010
- ISSCC 2010
Flip-flop upsets from single-event-transients in 65 nm clock circuits
- Larry Wissel
- David F. Heidel
- et al.
- 2009
- IEEE TNS
On-chip circuit for monitoring frequency degradation due to NBTI
- Kevin Stawiasz
- Keith A. Jenkins
- et al.
- 2008
- IRPS 2008
A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing
- Azeez J. Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
A sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2007
- VLSI Circuits 2007
A multi-mode power gating structure for low-voltage deep-submicron CMOS ICs
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2007
- IEEE TCAS-II
Fluctuation limits & scaling opportunities for CMOS SRAM cells
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2005
- IEDM 2005
Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2004
- ISLPED 2004
Experimental measurement of a novel power gating structure with intermediate power saving mode
- Suhwan Kim
- Stephen V. Kosonocky
- et al.
- 2004
- ISLPED 2004