Nikolaos Papandreou, Thomas Parnell, et al.
IMW 2016
For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications. The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write cycle of 176.7ns. In addition, a record high switching speed of 128ns with good resistance distribution is demonstrated with a super-fast Set material.
Nikolaos Papandreou, Thomas Parnell, et al.
IMW 2016
Win-San Khwa, Meng-Fan Chang, et al.
ISSCC 2016
Robert L. Bruce, Gloria Fraczak, et al.
SPIE Advanced Lithography 2017
Nanbo Gong, W. Chien, et al.
VLSI Technology 2020