ON THE IMPURITY PROFILES OF DOWN SCALED BIPOLAR TRANSISTORS.
D.D. Tang, G.P. Li, et al.
IEDM 1985
This paper describes the extension of “double-poly” self-aligned bipolar technology to include a silicon-filled trench with self-aligned cap oxide isolation, a p+ polysilicon defined epi-base lateral p-n-p, a p+ polysilicon defined self-aligned guard-ring Schottky-barrier diode, and p+ polysilicon resistors. Experimental circuits designed with 1.2-µm design rules have shown switching delays of as small as 73 ps for ECL circuits with FI = FO = 1. ISL circuits built with the same process on the same chip as the ECL circuits exhibit a sub-400-psswitching delay. The performance of the technology has also been demonstrated by a 5-kbit ECL SRAM with a 760-µm2 Schottky-clamped multi-emitter cell and 1.0-ns access time. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
D.D. Tang, G.P. Li, et al.
IEDM 1985
Tak H. Ning
ECS Meeting 2007
Tak H. Ning, Peter W. Cook, et al.
IEEE JSSC
C.T. Chuang, G.P. Li, et al.
IEEE T-ED