Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique

A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. A silicon-on-insulator (SOI) region surrounding the collector opening is used to minimize the collector window width, and to increase the thickness of the extrinsic base contact layer for a given device topography. This partial-SOI isolation structure can be combined with any type of emitter-base self-alined bipolar transistor structure.