Conference paper
Very high performance 50 nm CMOS at low temperature
S.J. Wind, L.T. Shi, et al.
IEDM 1999
A planar, triple-self-aligned, double-gate GET process is implemented where a unique sidewall source/drain structure permits self-aligned patterning of the back-gate layer after the source/drain (S/D) structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. Moreover, double-gate FET (DGFET) operation is demonstrated with good transport at both interfaces.
S.J. Wind, L.T. Shi, et al.
IEDM 1999
P. Solomon, K. Weiser
Journal of Applied Physics
J. Appenzeller, J.A. Del Alamo, et al.
Electrochemical and Solid-State Letters
B. Doris, Y. Zhang, et al.
VLSI Technology 2004