Electrical characterization of 3D Through-Silicon-Vias
- Fei Liu
- Xiaoxiong Gu
- et al.
- 2010
- ECTC 2010
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14 results for Fei Liu
A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid cu-adhesive bonding
- F. Liu
- R.R. Yu
- et al.
- 2008
- IEDM 2008
Dopant-segregation technique for leakage reduction and performance improvement in trigate transistors without raised source/drain epitaxy
- Fei Liu
- Zhen Zhang
- et al.
- 2014
- IEEE Electron Device Letters
Ultra low contact resistivities for CMOS beyond 10-nm node
- Zhen Zhang
- Siyuranga Obasa Koswatta
- et al.
- 2013
- IEEE Electron Device Letters
Subtractive W contact and local interconnect co-integration (CLIC)
- Fei Liu
- Benjamin Fletcher
- et al.
- 2013
- IITC 2013
Cu-based bonding technology for 3D integration applications
- K.N. Chen
- Zheng Xu
- et al.
- 2012
- 3DIC 2012
A 0.021 μm2 trigate SRAM cell with aggressively scaled gate and contact pitch
- Michael A. Guillorn
- Josephine Chang
- et al.
- 2011
- VLSI Technology 2011
Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding
- R.R. Yu
- F. Liu
- et al.
- 2009
- VLSI Technology 2009
Design and modeling methodology of vertical interconnects for 3DI applications
- Rachel Gordin
- David Goren
- et al.
- 2011
- IEEE Transactions on CPMT
Effect of spatial charge inhomogeneity on 1/f noise behavior in graphene
- Guangyu Xu
- Carlos M. Torres Jr.
- et al.
- 2010
- Nano Letters