Eloisa Bentivegna
Big Data 2022
A cost effective 28 nm CMOS Interconnect technology is presented for 28 nm node high performance and low power applications. Full entitlement of ultra low-k (ULK) inter-level dielectric is enabled. Copper wiring levels can be combined up to a total of 11 levels. The inter-level dielectric was optimized for low k-value and high strength. The feature profiles were optimized to enable defect-free metallization using conventional tools and processes. High yields and robust reliability were demonstrated. © 2011 Elsevier B.V. All rights reserved.
Eloisa Bentivegna
Big Data 2022
Sharee J. McNab, Richard J. Blaikie
Materials Research Society Symposium - Proceedings
Frank Stem
C R C Critical Reviews in Solid State Sciences
Biancun Xie, Madhavan Swaminathan, et al.
EMC 2011